In the art of radio communications, transmission power amplifiers are required to have higher linearity for higher-rate and larger-capacity communications. Requirements for linearity are determined according to the standards of various communication processes. One important linearity index employed in those standards is called error vector magnitude (EVM).
FIG. 1 is a diagram showing an example of a general demodulated signal. FIG. 1 shows ideal symbol 11, measured symbol 12, and error vector 13. Error vector 13 represents the difference between measured symbol 12 and ideal symbol 11.
The square mean of error vectors 13 of a plurality of sampled data is standardized by the average power P0 of ideal symbol 11, and an EVM is defined as the square root of the standardized value. If measured symbol 12 is represented as vector quantity c′ and ideal symbol 11 as vector quantity c, then the EVM value is expressed by the equation (1) shown below. In the equation (1), k is a variable representing a sample number, and N the number of samples.
                    EVM        =                                            1                                                P                  0                                ⁢                N                                      ⁢                                          ∑                                  k                  =                  1                                N                            ⁢                                                                                                                                    c                        ′                                            ⁡                                              (                        k                        )                                                              -                                          c                      ⁡                                              (                        k                        )                                                                                                              2                                                                        (        1        )            
Limit values for the EVM are directly or indirectly determined according to the communication standards. For example, IEEE Std. 802.11a, Part 11: wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed physical layer in the 5 GHz band, pp. 29, 1999 specifies that a relative constellation error in a communication mode of 54 Mbps shall be −25 dB or less. The relative constellation error of −25 dB or less is equivalent to an EVM value of 5.6% (=100×10(−25/20)%) or less.
GSM 05.05 V8.2.0—Digital cellular telecommunications system (phase 2+); radio transmission and reception, pp. 27, SEPTEMBER, 2000 specifies that with respect to EVM values in EDGE which is one of cellular phone standards, terminal devices shall satisfy an EVM value of 9% or less and base stations shall satisfy an EVM value of 7% or less.
FIG. 2 is a flowchart of a sequence according to a conventional general EVM evaluating method. As shown in FIG. 2, according to the conventional EVM evaluating method, a modulated signal is input to a system under test (step A1), and the modulated signal output from the system under test is measured (step A2). Then, the modulated signal is demodulated (step A3), and an error vector is extracted from the demodulated signal (step A4). The demodulated signal and the error vector are acquired at a plurality of sampling points.
Then, an average value of error vector power levels obtained at the respective sampling points is determined (step A5). Then, the average value of error vector power levels is divided by the average power level of an ideal demodulated signal, and the square root of the quotient is calculated as an EVM value (step A6).
The evaluation of the EVM value is completed according to the above process. However, if necessary, the evaluation of an EVM value may be repeated (step A7). For example, a parameter such as an average power level of the input modulated signal or a biasing condition for the system under test may be changed, and an EVM value may be evaluated according to the same process. Alternatively, the measurement may be repeated without changing the parameter.
A conventional circuit simulator, a conventional evaluating device, and a conventional EVM evaluating method for a communication circuit to be described below are basically based on the method shown in FIG. 2.
FIG. 3 is a block diagram showing an arrangement of a conventional circuit simulator with a function to calculate an EVM value. As shown in FIG. 3, the conventional circuit simulator has input unit 31, storage unit 33, data processor 34, and output unit 35.
Input unit 31 is a unit that is operable for entering information such as various data, etc., and may be a keyboard, for example. Storage unit 33 has modulating process storage 27, system-under-test storage 28, demodulating process storage 29, and extracted error vector storage 30. Modulating process storage 27 stores information of a modulating process that is entered from input unit 31. System-under-test storage 28 stores information of a system under test that is entered from input unit 31. Demodulating process storage 29 stores information of a demodulating process that is entered from input unit 31. Extracted error vector storage 30 stores information of an error vector that is extracted by data processor 34.
Data processor 34 performs a predetermined simulating process by executing a program. Data processor 34 realizes an arrangement having modulated signal generator 21, system-under-test model 1a, modulated signal evaluator 22, demodulator 23, error vector extractor 24, error vector averager 25, and EVM value calculator 26.
Output unit 35 is a unit for outputting information from data processor 34, and may be a display unit or a printer, for example. Output unit 35 has EVM value display 32.
The circuit simulator shown in FIG. 3 operates as follows: First, a modulating process is selected, and information of a model which reproduces operation of a generator for generating a modulated signal according to the modulating process is entered through input unit 31. The entered information about the modulating process is stored in modulating process storage 27. Information of a model which reproduces operation of a system under test is also entered through input unit 31. The entered information of the model of the system under test is stored in system-under-test storage 28. Information of a model of a demodulator based on a demodulating process which corresponds to the selected modulating process is entered through input unit 31. The entered information is stored in demodulating process storage 29.
Modulated signal generator 21 generates a numerical modulated signal based on the information stored in modulating process storage 27. The generated modulated signal is input to system-under-test model 1a. 
Based on the information of the model of the system under test which is stored in system-under-test storage 28, system-under-test model 1a performs a predetermined numerical calculation on the modulated signal output from modulated signal generator 21.
Modulated signal evaluator 22 evaluates the calculation that has been performed on the modulated signal by system-under-test model 1a. Demodulator 23 demodulates the modulated signal evaluated by modulated signal evaluator 22, based on the model of the demodulator stored in demodulating process storage 29. The modulated signal and the demodulated signal are acquired at a plurality of sampling points.
Error vector extractor 24 extracts an error vector from the demodulated signal produced by demodulator 23. Error vectors obtained at a plurality of sampling points are recorded in extracted error vector storage 30, if necessary.
Error vector averager 25 determines an average value of a plurality of error vectors extracted by error vector extractor 24.
EVM value calculator 26 calculates an EVM value by dividing the average power level of error vectors obtained by error vector averager 25 by the average power level of an ideal demodulated signal, and determining the square root of the quotient.
EVM value display 32 displays the EVM value calculated by EVM value calculator 26.
FIG. 4 is a block diagram showing an arrangement of a conventional measuring device with a function to evaluate an EVM value. As shown in FIG. 4, the conventional measuring device has modulated signal generating unit 50 and EVM value evaluating unit 51. EVM value evaluating unit 51 comprises demodulator 42, error vector extracting circuit 43, error vector averaging circuit 44, EVM value calculating circuit 45, and EVM value display circuit 46.
Modulated signal generator 41 generates a modulated signal and inputs the modulated signal to system 1 under test. Average power levels of modulated signals that are input to and output from system 1 under test are supplied respectively through couplers 47a, 47b and evaluated respectively by input power measuring unit 48 and output power measuring unit 49.
Demodulator 42 demodulates the modulated signal output from system 1 under test. Error vector extracting circuit 43 extracts error vectors from the demodulated signal.
Error vector averaging circuit 44 determines an average power of the error vectors. EVM value calculating circuit 45 divides the average power of the error vectors which has been obtained by error vector averaging circuit 44, by the average power level of an ideal demodulated signal according to the equation (1), and calculates the square root of the quotient as an EVM value. EVM value display circuit 46 displays the obtained EVM value.
The processing sequence from the demodulation to the display of the EVM value is carried out by EVM value evaluating unit 51.
FIG. 5 is a block diagram of a conventional reception circuit having a function to select a reception mode based on the evaluated EVM value. For example, JP-A No. 2004-56499 discloses a reception circuit having a mode selecting function as shown in FIG. 5. As shown in FIG. 5, reception circuit 87 comprises two antennas 81a, 81b corresponding to different reception modes, and two demodulators 82a, 82b. Antennas 81a, 81b receive modulated signals, and demodulators 82a, 82b demodulate the modulated signals. The demodulated signals from respective demodulators 82a, 82b are transmitted to received baseband signal processing circuit 83.
Received baseband signal processing circuit 83 processes the demodulated signals according to a predetermined signal processing process, and sends the processed demodulated signals to error vector extracting circuit 84. Error vector extracting circuit 84 extracts error vectors from the demodulated signals. Error vector averaging circuit 85 determines average power levels of the error vectors extracted by error vector extracting circuit 84.
Control circuit 86 calculates EVM values in the different reception modes received by the respective antennas 81a, 81b, from the average power levels according to the equation (1), compares the EVM values, and selects the reception mode with the lower EVM value for better signal quality.
FIG. 6 is a block diagram showing an arrangement of a conventional transmission/reception circuit having a function to generate a modulated signal for correcting a distortion of a system under test, based on the evaluated error vector. For example, JP-A No. 2002-9642 discloses a transmission/reception circuit having a function to correct a distortion-induced error as shown in FIG. 6. As shown in FIG. 6, transmitting/receiving circuit 69 comprises system 1 under test, modulated signal generator 61, control circuit 62, coupler 63, demodulator 64, error vector extracting circuit 65, received baseband signal processing circuit 66, and switcher 67.
During a period for performing an error control process, control circuit 62 controls switcher 67 to connect a path from system 1 under test to coupler 63. A modulated signal output from system 1 under test is now transmitted to demodulator 64.
Demodulator 64 demodulates the output modulated signal. Error vector extracting circuit 65 extracts an error vector from the demodulated signal from demodulator 64, and corrects a parameter of modulated signal generator 61 in order to minimize the error vector, based on the information of the extracted error vector.
When transmission/reception circuit 69 operates as described above, it corrects the error vector due to a distortion of system 1 under test for thereby improving the linearity thereof.
During a period for not performing the error control process, control circuit 62 controls switcher 67 to disconnect the path from system 1 under test to coupler 63. Now, conventional transmission/reception circuit 69 performs a transmission mode of operation using modulated signal generator 61, system 1 under test, and antenna 68 and a reception mode of operation using antenna 68, demodulator 64, and received baseband signal processing circuit 66.
The circuit shown in FIG. 6 serves to correct the distortion based on the error vector. However, the distortion can be corrected without using the error vector of the demodulated signal if an amplitude distortion and a phase distortion of the system under test can be measured. FIG. 7 is a block diagram showing an arrangement of a conventional circuit having a function to correct a distortion of a system under test.
For example, JP-A No. 2003-258560 discloses a circuit having a distortion correcting function as shown in FIG. 7. As shown in FIG. 7, the circuit comprises couplers 101a, 101b, delay circuit 102, square detecting circuit 103, A/D converter 104, table 105, D/A converters 106, 115, low-pass filters 107a, 107b, phase circuit 108, amplitude circuit 109, amplifier 110, distortion detecting circuit 112, table updating circuit 113, VCO control circuit 114, and VCO 116. A/D converter 104, table 105, D/A converters 106, 115, table updating circuit 113, VCO control circuit 114, and VCO 116 are constructed as digital processor 111.
An input signal divided by coupler 101a and detected by square detecting circuit 103 and an output signal divided by coupler 101b and detected by distortion detecting circuit 112 are input to digital processor 111. Based on the input signal, the output signal, and data stored in table 105 for distortion compensation, digital processor 111 controls phase circuit 108 and amplitude circuit 109 for correcting a distortion of amplifier 110. Table updating circuit 113 updates the data stored in table 105 based on the output signal from distortion detecting circuit 112.